The EN751221 family consists of the following devices:
| DSL | xPON | |
|---|---|---|
| Original | EN7512 @ 700Mhz | EN7521 @ 750Mhz |
| Updated | EN7513 @ 900Mhz | EN7526 @ 900Mhz |
From the perspective of the software, they are almost almost identical, with the major differences between the DSL and XPON chips being in the GPIO and PINMUX assignments.
| Confirmed | Interrupt # | Name | Description |
|---|---|---|---|
| 0 | UART_INT | UART interrupt | |
| 1 | PTM_B0_INT | DRAM illegal access interrupt | |
| 2 | SI_SWINT1_INT0 | Shadow of interrupt 7 | |
| 3 | SI_SWINT1_INT1 | Shadow of interrupt 8 | |
| 4 | TIMER0_INT | Timer 0 interrupt | |
| 5 | TIMER1_INT | Timer 1 interrupt | |
| 6 | TIMER2_INT | Timer 2 interrupt | |
| 7 | SI_SWINT_INT0 | MIPS34K software interrupt 0 | |
| 8 | SI_SWINT_INT1 | MIPS34K software interrupt 1 | |
| 9 | TIMER5_INT | Timer 3 (watchdog) interrupt | |
| 10 | GPIO_INT | GPIO controller interrupt | |
| 11 | PCM1_INT | PCM1 interrupt | |
| 12 | SI_PC1_INT | Shadow of interrupt 13 | |
| 13 | SI_PC_INT | MIPS34K performance counter interrupt | |
| 14 | APB_DMA0_INT | GDMA controller interrupt | |
| 15 | MAC1_INT, ESW_INT | Giga switch interrupt | |
| 16 | HSUART_INT | UART2 interrupt | |
| 17 | IRQ_RT3XXX_USB | USB host controller interrupt | |
| 18 | DYINGGASP_INT | Dying Gasp interrupt | |
| 19 | DMT_INT | xDSL DMT interrupt | |
| 20 | USB20_INT, UNUSED0_INT | USB 2.0 | |
| 21 | MAC_INT, FE_MAC_INT, CONFIG_QDMA_IRQ | QDMA LAN | |
| 22 | CONFIG_QDMA_IRQ | QDMA WAN | |
| 23 | PCIE_0_INT | PCIe Port0 interrupt | |
| 24 | PCIE_A_INT | PCIe Port1 interrupt | |
| 25 | PCIE_SERR_INT | PCIe Error interrupt | |
| 26 | XSLV0_INT, PTM_B1_INT | Unknown / Unused | |
| 27 | XSLV1_INT, SPI_MC_INT | Unknown / Unused | |
| 28 | XSLV2_INT, CRYPTO_INT, USB_INT | Crypto interrupt | |
| 29 | SI_TIMER1_INT | Shadow of interrupt 30 | |
| 30 | SI_TIMER_INT | High Precision Timer | |
| 31 | SWR_INT | Unknown / Unused | |
| 32 | BUS_TOUT_INT | Pbus timeout interrupt | |
| 33 | RESERVE_A_INT, PCM2_INT | Reserved | |
| 34 | RESERVE_B_INT | SLM interrupt | |
| 35 | RESERVE_C_INT | SPI controller interrupt | |
| 36 | AUTO_MANUAL_INT | CPU FDC interrupt0 | |
| 37 | CPU FDC interrupt1 | ||
| 38 | Reserved |